gr-verilog
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Make it possible to control the base directory for a given module
This can otherwise be problematic for calls to $readmemh etc.
Hi @gs-jgj Do you have an example testbench that has this issue or even better have you looked at adding this feature?
Haven't looked into it yet. A simple workaround is just to put absolute paths in all places that read data
But attached is a simple testcase that shows the issue testcase.zip
It will fail with %Error: lut.dat:0: $readmem file not found if you leave the files in some random directory.