Guido Sanchez

@zapta awesome work! It seems that everything is working properly. I will try those commands as soon as I have the FPGA with me again. To my understanding, SystemVerilog is...

I have always used apio prod and always downloaded it using pip. I will do that in order to use apio dev and check these features out. Is there anything...

@zapta I have modified some code on `apio/scons/scons_util.py` and as a result of those modifications, now `apio build` works with `.sv` files You can check https://github.com/gmsanchez/apio/commit/cfe6b315b9f08d0d10efbf40bba92469a54b41b4

@zapta I have added an example for the EDU-CIAA-FPGA, it is a simple 1-bit AND gate and is available here https://github.com/gmsanchez/apio/commit/e138c5b620746e317ff7f7c54dba0c3c52318e9b The module uses `logic` when defining the input and...

From the `iverilog` man page [https://linux.die.net/man/1/iverilog](https://linux.die.net/man/1/iverilog): > -g1995|-g2001|-g2001-noconfig|-g2005 Select the Verilog language generation to support in the compiler. This selects between IEEE1364-1995, IEEE1364-2001, or IEEE1364-2005. Normally, Icarus Verilog defaults to...

From what I understand, SystemVerilog is a super-set of Verilog. So, if we use a SystemVerilog enabled toolchain we could mix .sv and .v files. That being said, I really...

@zapta that is great! Is there any way I can help with that? Just let me know

Hi! I got it working by running these commands inside the `and-gate` directory ``` apio clean apio build yosys -m slang -f slang -p "show -format dot -colors 1 -prefix...

I have asked about that issue here: https://github.com/YosysHQ/oss-cad-suite-build/issues/133 In the meantime I will try to figure this out Thanks!

That's what I also think about mixing .sv and .v files. What I am not sure about is the level of maturity of each of the tools implied in the...