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fix iwdg example and add code to disable iwdg in halt
fix iwdg example and add code to disable iwdg in halt
When using the example to enable and use the iwdg i found that when i had my cpu enter halt the watchdog kept running and timed out even though i had enabled that the cpu should stop in halt mode.
I found looking at some legacy code that setting KR to 0xAA and not 0xCC fixed the problem.
Maybe the 0xAA is a copy paste error?
I have also added a function to disable watchdog in halt in the option bytes
Thanks for pointing this out to me!
Now I'm trying to understand and test your changes. Which specific STM8 variant are you using?
Intermediate update:
I have played around with a STM8S Discovery board to check your observation and proposed changes. Here is my current status:
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my code is pretty messy :-( However, I don't actively develop these device headers anymore, as all STM8 are now "not recommended for new designs". So much for the protocol... ;-)
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I confirm that with the original example IWDG is running in HALT mode with AWU -> IWDG triggers a reset in HALT mode :-(
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KR=0xCC starts IWDG via software (see RM0016 v14, section 14.3.1). Writing KR=0xAA only refreshes the counter, but does not start IWDG. I confirmed this experimentally
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So far I haven't found a way to deactivate IWDG in HALT mode (with AWU) -> need to ask in STM user forum
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IMHO your proposed function
disable_iwdg_in_halt()should work for (at least most) STM8L/AL. However:- STM8S/AF apparently lack the respective option bit (see datasheet)
- for STM8S/AF you also need to store the inverted NOPT, else the µC remains in a reset cycle
- you should only modify the option bits you need, not write the whole byte. Else you risk overwriting the WWDG options
Update:
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STM8S/AF doesn't support stopping IWDG in HALT mode, see here --> re-configure IWDG for 1s max. timeout, wake up via AWU periodically, service IWDG and re-enter HALT with AWU
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I will check your proposal for STM8L/AL using a STM8L Discovery Board. Stay tuned...