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RISC-V support?

Open ShouNichi opened this issue 1 year ago • 8 comments

By deleting line 155 (#include <immintrin.h>) in ggml.c, it works just fine on RISC-V. Maybe this can be added in Cmake?

ShouNichi avatar Mar 15 '23 16:03 ShouNichi

Why RISC-V64? There is no board yet that supports ratified vectorization (rvv) 1.0, only if you simulate it in QEMU 7+.

kassane avatar Mar 15 '23 17:03 kassane

Why RISC-V64? There is no board yet that supports ratified vectorization (rvv) 1.0, only if you simulate it in QEMU 7+.

Yeah, but it works on rv64gc... slowly(17s/token on visionfive2). I mean maybe we can make the code to compile without modification.

ShouNichi avatar Mar 15 '23 17:03 ShouNichi

Yeah, but it works on rv64gc... slowly(17s/token on visionfive2). I mean maybe we can make the code to compile without modification.

Did you test it on VisionFive2? Are there any tutorials available?

kfihihc avatar Mar 16 '23 02:03 kfihihc

Did you test it on VisionFive2? Are there any tutorials available?

As I mentioned before, just delete that one line and make. It should work right away.

ShouNichi avatar Mar 17 '23 01:03 ShouNichi

Why RISC-V64? There is no board yet that supports ratified vectorization (rvv) 1.0, only if you simulate it in QEMU 7+.

Yeah, but it works on rv64gc... slowly(17s/token on visionfive2). I mean maybe we can make the code to compile without modification.

We just tested on TH1520(16GB DDR) and D1(512MB DDR with some trick, not swap), TH1520 about 7s/token, and D1 about 3min/token due to memory.

Zepan avatar Mar 19 '23 07:03 Zepan

We just tested on TH1520(16GB DDR) and D1(512MB DDR with some trick, not swap), TH1520 about 7s/token, and D1 about 3min/token due to memory.

Nice test! (Hilarious 😅) https://twitter.com/SipeedIO/status/1637399800101629956

kassane avatar Mar 19 '23 16:03 kassane

Why RISC-V64? There is no board yet that supports ratified vectorization (rvv) 1.0, only if you simulate it in QEMU 7+.

I plan to add support for V extend acceleration, use vector intrinsics, it is compatible from 0.7.1 to 1.0

Zepan avatar Mar 20 '23 02:03 Zepan

Ref:

  • #288

kassane avatar Mar 20 '23 14:03 kassane

An #ifdef was added for RISC-V, closing issue

evanmiller avatar Jul 07 '23 13:07 evanmiller