monitor.breakWhen one half cycle too late

[Merilix]

As the title says. The sim should stop on specific signal in order to examine the cpu state when the condition is met. But the sim stops one half cycle later. I was trying to find which transistors where involved to build flags by looking for active pass transistors driving the ubus when the flags are stored in F register (reg_load_af and rl_wr active)

-- Not an issue but nice to have a little bit more room (MAX_NETS and MAX_TRANS constants) in order to add little test circuitry to segdefs and transdefs to provide combined break conditions.

[gdevic]

Will look into this when I am back in town. Thanks!

[Merilix]

I did my own build from your source. To fix the issue, I moved firing the onTick event down after the clock propagation. Not sure if this would interfere with other logic or if it should be moved further down to the very end of halfCycle() but works for me.

 src/ClassSimZ80.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/ClassSimZ80.cpp b/src/ClassSimZ80.cpp
index c64df07..c4333bc 100644
--- a/src/ClassSimZ80.cpp
+++ b/src/ClassSimZ80.cpp
@@ -203,10 +203,10 @@ inline void ClassSimZ80::halfCycle()
             handleIrq(); // Interrupt request/Ack cycle
     }
 
-    ::controller.onTick(m_hcycletotal);
-
     set(clk, "clk"); // Let the clock edge propagate through the chip
 
+    ::controller.onTick(m_hcycletotal);
+
     // After each half-cycle, populate the watch data
     int it;
     watch *w = ::controller.getWatch().getFirst(it);