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Published 20 hours ago • verified publisher icon gdevic
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An implementation of the Z80 CPU for Altera, Xilinx and Lattice FPGAs

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M1 asserted during bus acknowledge cycles

It seems like the M1 signal is pulled low during bus acknowledge, which would break DMA to IO devices, since they could interpret the I/O request as an interrupt acknowledge....

Noah1989 avatar Noah1989

Data pin latching

By Z-80 specification Data pins are sampled (latch-ed) in the beginning of T3 for Op-Code fetching or in the middle of T3 for Memory/IO read. By this project implementation it...

kopavel avatar kopavel

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verified publisher icon gdevic

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An implementation of the Z80 CPU for Altera, Xilinx and Lattice FPGAs

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