gbdev
Document that SB can be written after SC
My original comment from Discord
This is actually safe. There's a clock generator for the serial hardware unit that's fed by the 16384 Hz tap of DIV and divides it by 2 to create 8192 Hz. This divider is reset every time SC is written. And the first pulse that shifts bits happens next negative edge of the output of the divider. So you have like 63-127 M cycles from writing SC, depending on the current phase of DIV.
https://raw.githubusercontent.com/furrtek/DMG-CPU-Inside/master/Schematics/6_SERIAL_LINK.png
Todo: test and verify that emulators and for that matter real hardware actually handle it like it appears from the DMG-CPU-inside schematic.
From my own testing, modifying the Same Boy GB core in SuperJuniorSameDuck based on this information from Nitro fixed a bug with incorrect serial data transfer emulation.
The scenario was starting a transfer with rSC right before loading the serial payload data into rSB (typical convention is start after loading).
Before the fix the received serial data was incorrectly shifted off by one bit. After the fix the Mega Duck laptop system ROM interfacing with the keyboard, rtc, etc worked correctly in the emulator without needing rSC / rSB write order patching.
Example of starting the transfer before loading the data:
ld a, (SERIAL_XFER_ENABLE | SERIAL_CLOCK_INT) ; $81
ldh [rSC], a
ld a, [serial_tx_data__RAM_D023_]
ldh [rSB], a
