prjoxide
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gatecat
Documenting Lattice's 28nm FPGA parts
Seems Yosys/Prjoxide doesn't recognize the following primitive (found in the Radiant FPGA Libraries Reference Guide docs/web page), although Radiant does: ``` m.submodules += Instance("PCLKDIV", p_DIV_PCLKDIV = "X2", i_CLKIN = clk48.i,...
Context: trying to debug some issues encountered with using BRAM and amaranth fifos (the BRAM output is always 0 somehow) --needed a baseline, hence this example.
It seems to never end: ``` Info: iter=20608 wires=8032 overused=1 overuse=1 archfail=NA Info: iter=20609 wires=8032 overused=1 overuse=1 archfail=NA Info: iter=20610 wires=8032 overused=1 overuse=1 archfail=NA Info: iter=20611 wires=8032 overused=1 overuse=1 archfail=NA...
The `LRAM` clock-to-q timings seem pretty high (~10ns) as the datasheet says that the worst case fmax is around 130MHz. To investigate this I isolated `LRAM` fuzzing to a separate...
Lattice Nexus-family FPGAs include SEDC hardware for error detection and correction. A part of the sysCONFIG block, and documented [here](https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/PT2/FPGA-TN-02076-1-4-SED-SEC-User-Guide-for-Nexus-Platform.ashx?document_id=52788), it exposes a few inputs for configuration and a few...
I finally got my CrossLink-NX evaluation board (with a LICFL-40-8BG400C) and I put together a PCIe x1 to SMA board (https://github.com/teknoman117/PCIEX1-SMA) which I'm currently waiting on to arrive along with...
`prjoxide --version` gives me ``` prjoxide 0.1 ``` which doesn't help me figure out whether I'm getting an outdated version of prjoxide from Conda.
I'm filing this against prjoxide but I guess there is a good chance the issue actually lies in nextpnr somewhere. I don't know how to narrow it down further, sorry....
