c65gs
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gardners
FPGA-based C64 Accelerator / C65 like computer
This of course depends on issue #43. A link to the D81 file for testing would be helpful here...
If I am not wrong, the SD interface logic assume an internal buffer size of 512 byte. However, the SD card specification > 1.x extend possible block sizes from 512...
in viciv.hdl ``` unsigned(r_blnd) => antialiased_red, unsigned(g_blnd) => antialiased_green, unsigned(b_blnd) => antialiased_blue ``` reported as bad VHDL syntax by Vviado synthesis
Most of the machinery is in place, but it doesn't actually work. Consider simulation to see what is going on with the fetching and display. Make notes here about what...
In C64 mode the following code: POKE53280,0:POKE53281,1:POKE646,0:POKE199,1:FOR T=1 TO 800:?" ";:NEXT T shows a thin white line on the right side just before the border starts but after the screen...
Reported by a user: Second topic: C64 sprites (just basic sprites, but more difficult to demonstrate) Please enter the following code in C64 mode: POKE53280,6:POKE53281,0 POKE53248,23:POKE53249,55:POKE2040,64:POKE53287,1:POKE53269,1 FOR T=4096 TO 4159:POKE...
e.g., so that TXS, TYS cannot be split by an interrupt. Not currently implemented. For our design, this will in practice mean no interrupts after single byte instructions.
Required for Issue #27, as interface routine at $CAF4 waits for serial port to empty/fill?