CPU IPC is low: implement i-cache

[gardners]

Memory mapper makes this a bit interesting to do.

Current thoughts:

• 1K 4-way associative cache with random replacement.
• Need random(ish) bit sequence generator.
• The cache would hold 3 bytes of fetched instruction.
• Cache lookup would occur when setting state <= InstructionFetch, so that it would be possible to execute an instruction every cycle.
• Cache address would be 28-bit address minus lowest 10-bits mapped by cache location.
• When writing to a byte, we need to potentially invalidate three cache lines, as the byte could occur in one of three addresses.
• Simplest approach for invalidation is to clear cache valid flag for all three affected cache lines, including all four sets in the cache line. To do otherwise would require loading the cache lines to check which needs invalidation. This should not affect performance much, anyway.
• Structure cache as 4 256 x 4-way sub-caches, based on address bits (9 downto 2). That way the invalidation-on-write can happen in parallel to the three lines that need it.

[gardners]

First step is to intercept all state <= InstructionFetch transitions along with the target PC. To ensure consistency, the cache cannot be allowed to lookup immediately after a MAP, $01 or $D030 write, as those can change the memory map, and thus the expansion of the PC to 28-bit address.