CPU IPC is very low. Implement ZP cache to speed up ZP addressing modes

[gardners]

Currently CPU is about 1/2 the speed of a similarly clocked 6502, largely due to a single wait state on reading from chipram. This is incurred for each read, even if multiple reads are required in an instruction, and the reads could therefore be pipelined.

Implement a ZP cache for odd and even ZP addresses that can be used to resolve ZP indirect addresses in a single cycle.

[gardners]

The 4510 B register makes this a bit trickier, as ZP can be anywhere in the address space. It should be possible to make a small indirect-ZP cache that we invalidate whenever ZP is written to (including $01, and also $D030), since B could be mapping ZP to some where that has just been banked in or out), B is changed or MAP instruction is executed.