Confusing hyphen in std_logic_vector literals don't care with signed number

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Input

signal sig_0 <= std_logic_vector(3 downto 0) := "-0---";
signal sig_1 <= std_logic_vector(3 downto 0) := "-1---";

Expected Behavior

signal sig_0 <= std_logic_vector(3 downto 0) := "-0---";
signal sig_1 <= std_logic_vector(3 downto 0) := "-1---";

Actual Behavior

signal sig_0 <= std_logic_vector(3 downto 0) := " - 0---";
signal sig_1 <= std_logic_vector(3 downto 0) := " - 1---";