VHDLFormatter
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Some fixes and a new feature
Improve indentation around multiline assignments, comma fixup feature, plus some minor updates.
Let me know if you'd like me to create issues for the indentation fixes.
Thanks for this PR. I noticed that one unit test failed (indent assignment statement (with comment)
).
How do you handle this case?
CONSTANT Vcc : SIGNAL := --logic 1 constant
'1';
CONSTANT zero4 : bit_vector(0 TO 3) :=--test
('0', '0', '0', '0');
The expected behavior would be:
CONSTANT Vcc : SIGNAL := --logic 1 constant
'1';
CONSTANT zero4 : bit_vector(0 TO 3) := --test
('0', '0', '0', '0');
Sorry for the long delay, busy with other work stuff right now :/ I had failed to run the jest testcases so I missed this. I found the bug but while doing so uncovered an inconsistency in my approach that I'd like to fix before pushing another set of changes. Coming up soon!
I've added the jest into the github action. So if you merge master into your pr, github will check for you automatically.