chisel-testers

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update for chipsalliance/chisel3#1944

1

sequencer

Reduce the startup time for a Scala Unit-test by skipping Verilator compilation *and* design elaboration

1

To interface to an existing test-system, I would like to launch a test from the command line hundreds of times by passing different test-input vector files on the command line....

oharboe

Using the PeekPokeTester, I ran into an issue where the VCD output of some signals is wrong. This happens with signals which are a mix of combinatorial oepration after a...

phhorrein

Hi, Trying to get fst waveform instead of vcd waveform from verilator so that the execution time and waveform data size can be reduced. (currently runs hours and generates a...

hukangha

Clock is initialized at 1 instead of 0

1

Having main `clock` initialized at `1`instead of `0` will hide underlying issues at `t=0`. We discovered this issue while interconnecting some chisel code using synchronous reset with existing SV blackboxes...

johnsbrew

pokeAt with SyncReadMem

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I can't seem to use `pokeAt` with SyncReadMem. I get this: ``` [error] found : chisel3.core.SyncReadMem[chisel3.core.UInt] [error] required: chisel3.Mem[?] [error] (which expands to) chisel3.core.Mem[?] [error] pokeAt(tl.mem, 1, 15) ``` Is...

immesys

I got a problem in the test code of ComplexMemory. Here is the part of the code that cosed the error: ` "should work with verilator" in { iotesters.Driver.execute( args...

medabme

lenged

Poke in PeekPokeTester always happens at negedge???

9

I am testing a hardware that has streaming IO. From vcd waveform, it looks like that "poke" always happens at negedge. Is there a way to poke at the posedge...

dingqingy

Support for FST traces in verilator backend

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Introducing the ability to use FST format as the output format of `Verilator` trace dump, instead of the VCD format. FST is a more efficient trace format introduced by the...

kammoh