Vitis_with_100Gbps_TCP-IP
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fpgasystems
Mismatch between branch 2022.1 and its Development Target Platform
I tried building the project on the new vitis_2022_1 branch targeting U280, and it resulted in the following error on make all:
$ make all TARGET=hw DEVICE=/opt/xilinx/platforms/xilinx_u280_xdma_201920_3/xilinx_u280_xdma_201920_3.xpfm USER_KRNL=iperf_krnl USER_KRNL_MODE=rtl NETH=4
...
# if {[file exists "${xoname}"]} {
# file delete -force "${xoname}"
# }
# package_xo -xo_path ${xoname} -kernel_name ${krnl_name} -ip_directory ./packaged_kernel_${suffix} -kernel_xml ${xml_path}
WARNING: [Vivado 12-4404] The CPU emulation flow in v++ is only supported when using a packaged XO file that contains C-model files, none were found.
WARNING: [Vivado 12-12407] VLNV in kernel.xml does not match VLNV in any of the IPs specified with the ip_directory option: ethz.ch:kernel:cmac_krnl:1.0
INFO: [Common 17-206] Exiting Vivado at Fri Aug 26 05:29:19 2022...
mkdir -p ./build_dir.hw.xilinx_u280_xdma_201920_3
/opt/Xilinx/Vitis/2022.1/bin/v++ -t hw --platform /opt/xilinx/platforms/xilinx_u280_xdma_201920_3/xilinx_u280_xdma_201920_3.xpfm --save-temps --kernel_frequency 200 --advanced.param compiler.userPostSysLinkTcl=/home/ubuntu/sungsoo/Vitis_with_100Gbps_TCP-IP/scripts/post_sys_link.tcl --dk chipscope:network_krnl_1:m_axis_tcp_open_status --dk chipscope:network_krnl_1:s_axis_tcp_tx_meta --dk chipscope:network_krnl_1:m_axis_tcp_tx_status --dk chipscope:network_krnl_1:s_axis_tcp_open_connection --dk chipscope:network_krnl_1:m_axis_tcp_port_status --dk chipscope:network_krnl_1:m_axis_tcp_notification --dk chipscope:network_krnl_1:m_axis_tcp_rx_meta --dk chipscope:network_krnl_1:s_axis_tcp_read_pkg --dk chipscope:network_krnl_1:s_axis_tcp_listen_port --config ./kernel/user_krnl/iperf_krnl/config_sp_iperf_krnl.txt --config ./scripts/network_krnl_mem.txt --config ./scripts/cmac_krnl_slr.txt --report estimate --temp_dir ./build_dir.hw.xilinx_u280_xdma_201920_3 -l -o'build_dir.hw.xilinx_u280_xdma_201920_3/network.xclbin' _x.hw.xilinx_u280_xdma_201920_3/network_krnl.xo _x.hw.xilinx_u280_xdma_201920_3/iperf_krnl.xo _x.hw.xilinx_u280_xdma_201920_3/cmac_krnl.xo
WARNING: [v++ 60-1604] The supplied option 'dk' is deprecated. To standardize the command line, the preferred alternative is 'debug.chipscope','debug.list_ports', 'debug.protocol.
Option Map File Used: '/opt/Xilinx/Vitis/2022.1/data/vitis/vpp/optMap.xml'
****** v++ v2022.1 (64-bit)
**** SW Build 3524075 on 2022-04-13-17:42:45
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
WARNING: [v++ 60-1495] Deprecated parameter found: compiler.userPostSysLinkTcl. Please use this replacement parameter instead: compiler.userPostDebugProfileOverlayTcl
INFO: [v++ 60-1306] Additional information associated with this v++ link can be found at:
Reports: /home/ubuntu/sungsoo/Vitis_with_100Gbps_TCP-IP/build_dir.hw.xilinx_u280_xdma_201920_3/reports/link
Log files: /home/ubuntu/sungsoo/Vitis_with_100Gbps_TCP-IP/build_dir.hw.xilinx_u280_xdma_201920_3/logs/link
WARNING: [v++ 60-1216] --report/-r option has been deprecated. Please use --report_level/-R estimate to generate an estimate report file for software emulation
Running Dispatch Server on port: 37311
INFO: [v++ 60-1548] Creating build summary session with primary output /home/ubuntu/sungsoo/Vitis_with_100Gbps_TCP-IP/build_dir.hw.xilinx_u280_xdma_201920_3/network.xclbin.link_summary, at Fri Aug 26 05:29:42 2022
INFO: [v++ 60-1316] Initiating connection to rulecheck server, at Fri Aug 26 05:29:42 2022
INFO: [v++ 60-1315] Creating rulecheck session with output '/home/ubuntu/sungsoo/Vitis_with_100Gbps_TCP-IP/build_dir.hw.xilinx_u280_xdma_201920_3/reports/link/v++_link_network_guidance.html', at Fri Aug 26 05:29:43 2022
INFO: [v++ 60-895] Target platform: /opt/xilinx/platforms/xilinx_u280_xdma_201920_3/xilinx_u280_xdma_201920_3.xpfm
INFO: [v++ 60-1578] This platform contains Xilinx Shell Archive '/opt/xilinx/platforms/xilinx_u280_xdma_201920_3/hw/xilinx_u280_xdma_201920_3.xsa'
INFO: [v++ 74-78] Compiler Version string: 2022.1
ERROR: [v++ 60-1299] The specified platform is not supported. Platform 'xilinx_u280_xdma_201920_3.xpfm' (version 2019.2) is not supported by the current tool version (2022.1). By policy, platforms are supported for the remainder of the calendar year release plus the following calendar year release
ERROR: [v++ 60-703] Failed to finish linking
INFO: [v++ 60-1653] Closing dispatch client.
Makefile:147: recipe for target 'build_dir.hw.xilinx_u280_xdma_201920_3/network.xclbin' failed
make: *** [build_dir.hw.xilinx_u280_xdma_201920_3/network.xclbin] Error 1
There seems to be a mismatch between the Vitis and DTP versions specified in the README. (Vitis 2022.1, DTP xilinx_u280_xdma_201920_3)
Maybe the README needs an update, or is there a way that I can make the build work?
@xtfan Can you share your xbmgmt examine details? I've updated my XRT and DPTs (both Deployment and Development) to 2022.1 but running host fails... Thanks in advance!
xbmgmt examine:
$ xbmgmt examine
System Configuration
OS Name : Linux
Release : 4.15.0-192-generic
Version : #203-Ubuntu SMP Wed Aug 10 17:40:03 UTC 2022
Machine : x86_64
CPU Cores : 12
Memory : 32156 MB
Distribution : Ubuntu 18.04.6 LTS
GLIBC : 2.27
Model : To Be Filled By O.E.M.
XRT
Version : 2.13.479
Branch : 2022.1
Hash : 5e92a513c6950e79638b1a879ddb882da34fc683
Hash Date : 2022-06-25 02:08:32
XOCL : 2.13.479, 5e92a513c6950e79638b1a879ddb882da34fc683
XCLMGMT : 2.13.479, 5e92a513c6950e79638b1a879ddb882da34fc683
Devices present
BDF : Shell Platform UUID Device ID Device Ready*
[0000:2b:00.0] : xilinx_u280_gen3x16_xdma_base_1 283BAB8F-654D-8674-968F-4DA57F7FA5D7 mgmt(inst=11008) Yes
* Devices that are not ready will have reduced functionality when using XRT tools
Run result:
$ ./host ../build_dir.hw.xilinx_u280_gen3x16_xdma_1_202211_1/network.xclbin
Found Platform
Platform Name: Xilinx
INFO: Reading ../build_dir.hw.xilinx_u280_gen3x16_xdma_1_202211_1/network.xclbin
Loading: '../build_dir.hw.xilinx_u280_gen3x16_xdma_1_202211_1/network.xclbin'
Trying to program device[0]: xilinx_u280_gen3x16_xdma_base_1
Device[0]: program successful!
local_IP:a01d498, boardNum:0
XRT build version: 2.13.479
Build hash: 5e92a513c6950e79638b1a879ddb882da34fc683
Build date: 2022-06-25 02:08:32
Git branch: 2022.1
PID: 18860
UID: 1000
[Tue Sep 13 07:12:05 2022 GMT]
HOST: [hostname]
EXE: [base_dir]/host/host
[XRT] ERROR: std::bad_alloc
host/iperf_krnl/host.cpp:159 Error calling err = network_kernel.setArg(4, buffer_r2), error code is: -5
Hi，I also encounter this error. I change the size of the buffer in the host.cpp to get rid of this error.
@xtfan Thanks! May I ask exactly how you changed the size? I tried increasing the buffer size by 2x or more, but this didn't help the situation.
@lomotos10 When I change the DATA_SIZE to be 6250000, the error is gone. But I don't know the negative impact of this change.
@xtfan Thank you, now ./host works. To be clear, does the application still work for you? (e.g. iperf for iperf_krnl)
@lomotos10 I have no any 100G NIC or switch for experiment so I just connect two U280 directly that run the same iperf_krnl. It seems that each FPGA card can send and receive packages from each other according to the debug ila. But I can't determine whether each of them is working correctly. Actually, I have tried corundum project (opensource) as a 100G NIC. However, the corundum failed to establish link with the 100G cmac in this project. Until now, I still can't run iperf on the server to test the iperf_krnl due to the lack of 100G NIC.
I'm using U250 with Vitis 2022.2 and I encounter this same error. Is there a way to fix this error. Using U280 give the same error.
When I contacted the developers by mail I was redirected to the https://github.com/fpgasystems/fpga-network-stack project because that project is being maintained, unlike this one.