Vitis_with_100Gbps_TCP-IP
Vitis_with_100Gbps_TCP-IP copied to clipboard
fpgasystems
100 Gbps TCP/IP stack for Vitis shells
I tried building the project on the new `vitis_2022_1` branch targeting U280, and it resulted in the following error on `make all`: ```shell $ make all TARGET=hw DEVICE=/opt/xilinx/platforms/xilinx_u280_xdma_201920_3/xilinx_u280_xdma_201920_3.xpfm USER_KRNL=iperf_krnl USER_KRNL_MODE=rtl...
Hi, Just wonder how hard it is to port to U250. Would U250 be supported in the future? Best, Yang
[10:33:50] Starting bitstream generation.. [10:49:24] Run vpl: Step impl: Failed [10:49:25] Run vpl: FINISHED. Run Status: impl ERROR ===>The following messages were generated while Compiling (bitstream) accelerator binary: network Log...
Don't know why you put 0 in sys_reset but clearly many logic and the cmac ip depend on this signal to be initialized
I've done built this project on u280 platform. however when opening the vivado project generated from vitis/v++, I can not find the top module name "pfm_top_wrapper". Also, I see that...
I've spent weeks on porting the whole project to Alveo U50 but its still doesnt work. I'd like to know if there anybody who port it successfully and how? Best.
Hey, The Readme states that this network stack can also be used in OpenCL. I would really like to give it a shot. Unfortunately, the repository seems not to contain...
May I ask what adjustments I need to make if I want to deploy on u200 and use vitis2020
I want to build a 100G tcp/ip server in fpga, so pc client can send data to server and server can loop back that data to pc client. I have...
Trying to build project but getting errors Vitis 2022.1 Ubuntu 22.04 u50 platform - xilinx_u50_gen3x16_xdma_5_202210_1 Steps to reproduce - 1. git clone https://github.com/fpgasystems/Vitis_with_100Gbps_TCP-IP.git 2. cd Vitis_with_100Gbps_TCP-IP 3. git submodule update...
