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verified publisher icon fpgadeveloper

build script update

Open bigbrett opened this issue 9 years ago • 1 comments

Hi Jeff,

Looks like Xilinx must have changed the name of the PS reset block in the netlist. In order for this project to successfully build, you need to replace all instances of *rst_ps7_0_100M* with *rst_processing_system7_0_100M* in Vivado/src/bd/design_1.tcl.

bigbrett avatar Dec 05 '16 17:12 bigbrett

Hi Brett,

I think it should be the other way around Brett. Are you using Vivado 2016.3? It should build fine with 2016.3.

fpgadeveloper avatar Dec 05 '16 19:12 fpgadeveloper