fmadio

probably want to look at L3 miss rate and/or DDR Rd counters as it steps. Gen3 x16 will max out ~ 112Gbps after the encoding overhead in practice.

Yeah 64/66 encoding is not connected to this at all, there`s absolutely no flow control when your at that level, its 103.125Gbps or 0 Gbps with nothing in between. There...

Yup its probably QPI / L3 / DDR some where some how. Assuming the Tx payloads are unique memory locations the plateau is the PCIe requestor hitting a 64B line...

Cool, one thing totally forgot is 112Gbps is PCIe Posted Write bandwidth. As our capture devices is focused on Write to DDR I have not tested what the Max DDR...

Also, for the Max PCIe/MLX4 green line. Looks like your off by 1 64B line some how ?

A few things. 1) Pretty much all devices support "PCIe Extended Tags" which add a few more bits so you can have alot more transactions in flight at any one...

HDL these days is almost entirely packet based, all the flow control and processing inside those fancy asic`s are mostly packet based. So all the same algos are there, different...

wow im blinded by the shinyness, very cool. R2PCIe.\* looks interesting, would have to read the manual to work out what each actually mean.

Because packets are always less than 14bits on the physical network. your seeing larger sized packets because segment offloading is enabled on the NIC. On Tue, Apr 13, 2021, 19:20...

correct, we use the application for running analysis on real wore traffic On Tue, Apr 13, 2021, 19:48 Michael Brade ***@***.***> wrote: > I see. So am I not supposed...