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simd: riscv: implement RVV intrinsics
In RISC-V intrinsics, RVV (RISC-V "Vector") extensions are existing. In this PR, I experimented to implement RVV extensions and got succeeded to pass internal and runtime tests with turning on this RVV extensions. This PR uses RVV v0.11 intrinsics.
Some of the RVV extensions are not corresponding one-by-one to NEON or SSE2.
Plus, vuint8m1_t and vuint32m1_t types do not have fixed size.
So, I assumed the fixed lengths for them is 16 like as the result of sizeof(__m128i) or sizeof(uint8x16_t).
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Fluent Bit is licensed under Apache 2.0, by submitting this pull request I understand that this code will be released under the terms of that license.
I think we need to run the package tests once #9751 is merged to confirm all builds are good.