Vitis HLS RTL Blackbox interface support

[Ansaya]

Generation of RTL Blackbox interface requires generating an accelerator with specific interface for control signals and parameters. Control signals require ap_ctrl_hs or ap_ctrl_chain interface generation as described in Vitis HLS User Guide. Paramters interface restrictions are described in Blackbox functions summary and should be already implemented in Bambu HLS from the --generate-interface=INFER option. Finally, RTL Blackbox model integration requires a JSON description of the module interface following this specification.

• [ ] Extend --generate-interface command line option with AP_CTRL_HS and AP_CTRL_CHAIN modes (must enable INFER mode too)
• [ ] Use --export-ip option to require additional files generation for the integration with the vendor tool
• [ ] Add generation of RTL Blackbox JSON to support the integration of generated accelerator in Vitis HLS designs