Specification for VLQ should be explicit on 7-bit bytes starting from the right

[udhos]

I think the VLQ specification should be more explicit about building 7-bit bytes starting from the right (least significant bits):

Correct order: start from the right (least significant bits): 32 bit input = (4-bits) (7-bits) (7-bits) (7-bits) (7-bits)

Wrong order: start from the left (most significant bits): 32 bit input = (7-bits) (7-bits) (7-bits) (7-bits) (4-bits)

Problem specification: https://github.com/exercism/problem-specifications/blob/master/exercises/variable-length-quantity/description.md

Of course the student can find the correct order by looking at the test cases, but is there a reason to not being more explicit?