Ewen McNeill

\o/ 8kB `0x2000` RAM works with the newer (first broken) commits. It doesn't boot to MicroPython, only to the BIOS, because it can't find anything to boot from, but that's...

@niklasnisbeth I've CC'd you (and @mithro) on https://github.com/enjoy-digital/litex/issues/417; hope that's okay. @niklasnisbeth If you do have a way of trying the iCE40 HK8K with the `sram` size forced to 0x2000...

FTR, the default `integrated_sram_size` is coming from `litex` `soc_core.py`: https://github.com/enjoy-digital/litex/blob/b5bddc2332bc701fbcfe028faf0980a3e6641320/litex/soc/integration/soc_core.py#L266-L268 and is also repeated at: https://github.com/enjoy-digital/litex/blob/b5bddc2332bc701fbcfe028faf0980a3e6641320/litex/soc/integration/soc_core.py#L71-L72 both with hard coded values (I'm not sure why it doesn't follow DRY). These...

> both with hard coded values (I'm not sure why it doesn't follow DRY). Ah, now I look at the locations, one is the `__init__()` default arguments, and one is...

The arguments to the target come via: https://github.com/timvideos/litex-buildenv/blob/d6cffe26a17af015821142a8b199fc6460f149d8/make.py#L55-L57 which filters out the command line parsed args via: https://github.com/enjoy-digital/litex/blob/b5bddc2332bc701fbcfe028faf0980a3e6641320/litex/soc/integration/soc_sdram.py#L65-L72 https://github.com/enjoy-digital/litex/blob/b5bddc2332bc701fbcfe028faf0980a3e6641320/litex/soc/integration/soc_core.py#L300-L314 and turns it into a pair of `dict`s which are mashed...

> About the only thing I can think of to do is to try setting per target defaults via the target `Makefile`, and then do something like what is done...

(I wrote most of this last night, but reaiised today that I hadn't actually added it to the ticket.) \o/ I got MicroPython to boot. It needed one more tweak...

@niklasnisbeth Now that #348 is merged, which updates to a litex which has working non-power-of-2 memory and a working set of compile flags, I think the iCE40 HX8K EVB is...

Thanks for testing. `lm32.minimal` is basically what I was testing with on a TinyFPGA BX, so that's the most likely to work (I suspect `vexriscv.minimal` should work too, but I...

@cklarhorst Thanks for writing this up into a worked example. It looks like a very useful combination of "reference context" and code examples to point people at when understanding how...