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verified publisher icon ethindp

Timer via LAPIC

Open ethindp opened this issue 4 years ago • 0 comments

The local APIC contains a timer that is controlled by the initial count, current count, and divide configuration registers (offsets 380h, 390h, and 3E0h). The kernel currently only uses the TSC as a timer, but the LAPIC should be a reasonable fallback should this mechanism fail. We may also wish to investigate switching to the HPET if available.

ethindp avatar Sep 10 '21 21:09 ethindp