Compilation failed if dl::image::crop_and_resize(...) is used (AIV-642)

[Mr-Techtron]

using the latest master version, I am unable to compile the project after using the function "crop_and_resize". It shows "undefined reference to `void dl::image::crop_and_resize(unsigned short*, int, int, int, int, int, int, unsigned short*, int, int, int, int, int, int, int, dl::image::resize_type_t, int)'"

[esp-qing]

Hi, according to your requirements [256 kHz clock, mono, short 16 bit], this is the corresponding lib file based on idf version v5.2. [libbtdm_app.zip] The requirement about slave role can be configured in esp-idf. If you have any questions, feel free to ask.

[Ageofenigma]

It builds but esp_bt_controller_init returns "ESP_ERR_INVALID_ARG"

[esp-qing]

This lib file corresponds to esp-idf version 5.2.1. Could you please confirm which version of esp-idf you are using? You can view the log output from the compilation of the previous lib file.

[Ageofenigma]

idf.py --version shows ESP-IDF v5.2.1-dirty

[esp-qing]

Hi, this is the new lib file corresponding to idf version 5.2.1(commit a322e6bd), please try again. libbtdm_app.zip

[Ageofenigma]

It works thanks, but I figured out that the SimCom clock is 2048 KHz and looks like this: Could you change the clock to 2048 KHz? Will it work for the waveform like this?

[Ageofenigma]

Is it possible to rebuild it to 2048 KHz clock?

[esp-qing]

Hi, the default synchronization clock of esp-idf is 8kHZ, and the default data clock is 256kHZ. I guess the clock you want to modify is the data clock. There has never been a requirement to modify the clock before. Sorry, after trying, It cannot be directly modified to 2048kHZ at the moment and It will take some time to improve this feature. Maybe you can try modifying the SimCom clock? If you have any further questions please feel free to ask.