esp-hal SPI Slave for ESP32 / ESP32-S2

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Pull Request Details 📖

Description

This completes support for SPI Slave by adding support for ESP32 and ESP32-S2 (see #469)

Testing

Run the spi_slave_dma example on ESP32, ESP32-S2 and at least one of the others

Apr 26 '24 15:04 bjoernQ

@SergioGasquez or @playfulFence guys, could you please try to run this example on ESP32?

Apr 29 '24 12:04 JurajSadel

Not sure if the outputs are right but here are the results.

ESP32 required some pins modifications since Im using ESP32-DevKitC V4:

Diff

--- a/examples/src/bin/spi_slave_dma.rs
+++ b/examples/src/bin/spi_slave_dma.rs
@@ -64,8 +64,8 @@ cfg_if::cfg_if! {
     if #[cfg(any(feature = "esp32", feature = "esp32s2"))] {
         const MASTER_CS: u8 = 18;
         const MASTER_MOSI: u8 = 16;
-        const MASTER_SCLK: u8 = 0;
-        const MASTER_MISO: u8 = 5;
+        const MASTER_SCLK: u8 = 26;
+        const MASTER_MISO: u8 = 25;
     } else {
         const MASTER_CS: u8 = 9;
         const MASTER_MOSI: u8 = 8;
@@ -85,15 +85,15 @@ fn main() -> ! {
     cfg_if::cfg_if! {
         if #[cfg(any(feature = "esp32", feature = "esp32s2"))] {
                 let slave_sclk = io.pins.gpio2;
-                let mut master_sclk = io.pins.gpio0.into_push_pull_output();
+                let mut master_sclk = io.pins.gpio26.into_push_pull_output();
 
                 let slave_miso = io.pins.gpio4;
-                let master_miso = io.pins.gpio5.into_floating_input();
+                let master_miso = io.pins.gpio25.into_floating_input();
 
-                let slave_mosi = io.pins.gpio15;
+                let slave_mosi = io.pins.gpio17;
                 let mut master_mosi = io.pins.gpio16.into_push_pull_output();
 
-                let slave_cs = io.pins.gpio17;
+                let slave_cs = io.pins.gpio19;
                 let mut master_cs = io.pins.gpio18.into_push_pull_output();
             } else {
                 let slave_sclk = io.pins.gpio0;

ESP32 output

esp-hal on  spi-slave-esp32-esp32s2 [!] via 🦀 v1.80.0-nightly 
❯ cargo xtask run-example esp-hal esp32 spi_slave_dma
    Finished `dev` profile [unoptimized + debuginfo] target(s) in 0.02s
     Running `target/debug/xtask run-example esp-hal esp32 spi_slave_dma`
[2024-04-29T12:49:04Z WARN  xtask] Package 'esp-hal' specified, using 'examples' instead
[2024-04-29T12:49:04Z INFO  xtask] Building example '/home/sergio/Documents/Espressif/tests/esp-hal/examples/src/bin/spi_slave_dma.rs' for 'esp32'
[2024-04-29T12:49:04Z INFO  xtask] Package: "src/bin/spi_slave_dma.rs"
    Finished release [optimized + debuginfo] target(s) in 0.09s
     Running `espflash flash --monitor target/xtensa-esp32-none-elf/release/spi_slave_dma`
[2024-04-29T12:49:04Z INFO ] Serial port: '/dev/ttyUSB0'
[2024-04-29T12:49:04Z INFO ] Connecting...
[2024-04-29T12:49:04Z INFO ] Using flash stub
[2024-04-29T12:49:06Z WARN ] Setting baud rate higher than 115,200 can cause issues
Chip type:         esp32 (revision v3.1)
Crystal frequency: 40 MHz
Flash size:        8MB
Features:          WiFi, BT, Dual Core, 240MHz, VRef calibration in efuse, Coding Scheme None
MAC address:       b0:b2:1c:b4:59:24
App/part. size:    92,256/4,128,768 bytes, 2.23%
[2024-04-29T12:49:06Z INFO ] Segment at address '0x1000' has not changed, skipping write
[2024-04-29T12:49:06Z INFO ] Segment at address '0x8000' has not changed, skipping write
[00:00:00] [========================================]      23/23      0x10000                                                                                                                                                                       [2024-04-29T12:49:07Z INFO ] Flashing has completed!
Commands:
    CTRL+R    Reset chip
    CTRL+C    Exit

���������������������:46

rst:0x1 (POWERON_RESET),boot:0x1a (SPI_FAST_FLASH_BOOT)
configsip: 0, SPIWP:0xee
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:DIO, clock div:2
load:0x3fff0030,len:7104
load:0x40078000,len:15576
load:0x40080400,len:4
ho 8 tail 4 room 4
load:0x40080404,len:3876
entry 0x4008064c
0x4008064c - core::ptr::const_ptr::<impl *const T>::offset
    at /home/sergio/.rustup/toolchains/esp/lib/rustlib/src/rust/library/core/src/ptr/const_ptr.rs:469
I (31) boot: ESP-IDF v5.1-beta1-378-gea5e0ff298-dirt 2nd stage bootloader
I (31) boot: compile time Jun  7 2023 07:48:23
I (33) boot: Multicore bootloader
I (37) boot: chip revision: v3.1
I (41) boot.esp32: SPI Speed      : 40MHz
I (46) boot.esp32: SPI Mode       : DIO
I (50) boot.esp32: SPI Flash Size : 4MB
I (55) boot: Enabling RNG early entropy source...
I (60) boot: Partition Table:
I (64) boot: ## Label            Usage          Type ST Offset   Length
I (71) boot:  0 nvs              WiFi data        01 02 00009000 00006000
I (79) boot:  1 phy_init         RF data          01 01 0000f000 00001000
I (86) boot:  2 factory          factory app      00 00 00010000 003f0000
I (94) boot: End of partition table
I (98) esp_image: segment 0: paddr=00010020 vaddr=3f400020 size=01c8ch (  7308) map
I (109) esp_image: segment 1: paddr=00011cb4 vaddr=3ffb0000 size=00004h (     4) load
I (115) esp_image: segment 2: paddr=00011cc0 vaddr=40080000 size=01b4ch (  6988) load
I (126) esp_image: segment 3: paddr=00013814 vaddr=00000000 size=0c804h ( 51204) 
I (150) esp_image: segment 4: paddr=00020020 vaddr=400d0020 size=06814h ( 26644) map
I (161) boot: Loaded app from partition at offset 0x10000
I (161) boot: Disabling RNG early entropy source...
Iteration 1
Do `dma_transfer`
slave got [0, 0, 0, 0, 0, 0, 0, 0, 0, 0] .. [0, 0, 0, 0, 0, 0, 0, 0, 0, 0], master got [0, fd, fc, fb, fa, f9, f8, f7, f6, f5] .. [8b, 8a, 89, 88, 87, 86, 85, 84, 83, 0]
Do `dma_read`
slave got [0, 0, 0, 0, 0, 0, 0, 0, 0, 0] .. [0, 0, 0, 0, 0, 0, 0, 0, 0, 0]
Do `dma_write`
master got [0, fd, fc, fb, fa, f9, f8, f7, f6, f5] .. [8b, 8a, 89, 88, 87, 86, 85, 84, 83, 0]

Iteration 2
Do `dma_transfer`
slave got [0, 0, 0, 0, ff, ff, ff, ff, ff, ff] .. [0, 0, 0, 0, 0, 0, 0, 0, 0, 0], master got [1, fd, fc, fb, fa, f9, f8, f7, f6, f5] .. [8b, 8a, 89, 88, 87, 86, 85, 84, 83, 1]
Do `dma_read`
slave got [0, 0, 0, 0, ff, ff, ff, ff, ff, ff] .. [0, 0, 0, 0, 0, 0, 0, 0, 0, 0]
Do `dma_write`
master got [1, fd, fc, fb, fa, f9, f8, f7, f6, f5] .. [8b, 8a, 89, 88, 87, 86, 85, 84, 83, 1]

Iteration 3
Do `dma_transfer`
slave got [0, 0, 0, 0, ff, ff, ff, ff, ff, ff] .. [0, 0, 0, 0, 0, 0, 0, 0, 0, 0], master got [2, fd, fc, fb, fa, f9, f8, f7, f6, f5] .. [8b, 8a, 89, 88, 87, 86, 85, 84, 83, 2]
Do `dma_read`
slave got [0, 0, 0, 0, ff, ff, ff, ff, ff, ff] .. [0, 0, 0, 0, 0, 0, 0, 0, 0, 0]
Do `dma_write`
master got [2, fd, fc, fb, fa, f9, f8, f7, f6, f5] .. [8b, 8a, 89, 88, 87, 86, 85, 84, 83, 2]

Iteration 4
Do `dma_transfer`
slave got [0, 0, 0, 0, ff, ff, ff, ff, ff, ff] .. [0, 0, 0, 0, 0, 0, 0, 0, 0, 0], master got [3, fd, fc, fb, fa, f9, f8, f7, f6, f5] .. [8b, 8a, 89, 88, 87, 86, 85, 84, 83, 3]
Do `dma_read`
slave got [0, 0, 0, 0, ff, ff, ff, ff, ff, ff] .. [0, 0, 0, 0, 0, 0, 0, 0, 0, 0]
Do `dma_write`
master got [3, fd, fc, fb, fa, f9, f8, f7, f6, f5] .. [8b, 8a, 89, 88, 87, 86, 85, 84, 83, 3]

Iteration 5
Do `dma_transfer`
slave got [0, 0, 0, 0, ff, ff, ff, ff, ff, ff] .. [0, 0, 0, 0, 0, 0, 0, 0, 0, 0], master got [4, fd, fc, fb, fa, f9, f8, f7, f6, f5] .. [8b, 8a, 89, 88, 87, 86, 85, 84, 83, 4]
Do `dma_read`
slave got [0, 0, 0, 0, ff, ff, ff, ff, ff, ff] .. [0, 0, 0, 0, 0, 0, 0, 0, 0, 0]
Do `dma_write`
master got [4, fd, fc, fb, fa, f9, f8, f7, f6, f5] .. [8b, 8a, 89, 88, 87, 86, 85, 84, 83, 4]

On S2, I used the default pins:

ESP32-S2 Output

``` I (135) boot: Loaded app from partition at offset 0x10000 I (135) boot: Disabling RNG early entropy source... Iteration 1 Do `dma_transfer` slave got [0, 1, 2, 3, 4, 5, 6, 7, 8, 9] .. [73, 74, 75, 76, 77, 78, 79, 7a, 7b, 0], master got [0, fd, fc, fb, fa, f9, f8, f7, f6, f5] .. [8b, 8a, 89, 88, 87, 86, 85, 84, 83, 0] Do `dma_read` slave got [0, 1, 2, 3, 4, 5, 6, 7, 8, 9] .. [73, 74, 75, 76, 77, 78, 79, 7a, 7b, 0] Do `dma_write` master got [0, 0, 0, 0, 0, 0, 0, 0, 0, 0] .. [0, 0, 0, 0, 0, 0, 0, 0, 0, 0]

Iteration 2 Do dma_transfer slave got [f9, 80, 81, 82, 83, 84, 85, 86, 87, 88] .. [ff, ff, ff, ff, ff, ff, ff, ff, ff, ff], master got [0, fc, ff, f7, ff, e3, f1, ef, ff, a7] .. [0, 0, 0, 0, 0, 0, 0, 0, 0, 0] Do dma_read slave got [1, 1, 2, 3, 4, 5, 6, 7, 8, 9] .. [73, 74, 75, 76, 77, 78, 79, 7a, 7b, 1] Do dma_write master got [1, fd, fc, fb, fa, f9, f8, f7, f6, f5] .. [8b, 8a, 89, 88, 87, 86, 85, 84, 83, 1]

Iteration 3 Do dma_transfer slave got [2, 1, 2, 3, 4, 5, 6, 7, 8, 9] .. [73, 74, 75, 76, 77, 78, 79, 7a, 7b, 2], master got [2, fd, fc, fb, fa, f9, f8, f7, f6, f5] .. [8b, 8a, 89, 88, 87, 86, 85, 84, 83, 2] Do dma_read slave got [2, 1, 2, 3, 4, 5, 6, 7, 8, 9] .. [73, 74, 75, 76, 77, 78, 79, 7a, 7b, 2] Do dma_write master got [2, fd, fc, fb, fa, f9, f8, f7, f6, f5] .. [8b, 8a, 89, 88, 87, 86, 85, 84, 83, 2]

Iteration 4 Do dma_transfer slave got [3, 1, 2, 3, 4, 5, 6, 7, 8, 9] .. [73, 74, 75, 76, 77, 78, 79⏎

</details>

Apr 29 '24 13:04 SergioGasquez

this will be taken over by @JurajSadel

May 02 '24 06:05 bjoernQ

Closing this: https://github.com/esp-rs/esp-hal/pull/1562

May 17 '24 14:05 JurajSadel

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SPI Slave for ESP32 / ESP32-S2

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