TinyGarble
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esonghori
TinyGarble: Logic Synthesis and Sequential Descriptions for Yao's Garbled Circuits
Hi, I'm following the instructions for Yosys: https://github.com/esonghori/TinyGarble/tree/master/circuit_synthesis, but there is no file named `benchmark.v` throughout the repo. Did I miss something?
Hello, I'm using Yosys to read and make the synthesis of the Division Verilogs. However, for these verilogs, the "hierarchy -check -top top_module" step is not working. As so, the...
I am having problems using Yosys in your workflow. I linked in the circuit_synthesis/lib/asic_cell_yosys_extended.lib file and removed all of the /^\s*\(\*/ comment lines in the synthesized (netlist) output. (These steps...
It would really help to have the original Verilog files used to synthesize the provided netlists. This would allow users to experience the end-to-end workflow more easily.
The SCD documentation says there are seven values in the first line of the flag. But all of the included files have 10 values. The code names these values in...
Hello, first thanks for developing this MPC project. I followed the compilation instruction but the `make` step failed with a bunch of "incomplete type" errors. The first such error looks...
can u give more examples about how to use all the functions of tinygarble, like compare, sum, aes, etc i run the hamming example, and get the right result. but...
Hi, Thank you for the great library! I want to use multi-dimensional input and output arrays in the setup [without reshaping to 1-D]. For this, I'm using system verilog instead...
Hi, I just tried compiling/running the code, but the provided example fails. ``` ./TinyGarble --alice --scd_file bin/scd/netlists/hamming_32bit_32cc.scd --input FF55AA77 --log2std garbled_circuit_main.cpp:268 INFO: Open Alice's server on port: 1234 scd.cpp:49 ERROR:...
Hi, I was trying to execute a simple circuit with flip-flops, as shown below: ``` input clk, rst; input [3:0] g_input, e_input; wire [3:0] g_input, e_input; output [3:0] o; reg...
