Questasim simulation instruction fetch error IbexInstrLSBsKnown

[benoitdenkinger]

When using the default boot option (i.e., jtag) with questasim, if the instruction at the last address is executed (and the text section last address does not align with a multiple 0x1000), the next address is fetched. It produces an error as it is empty (X). The error is harmless as this instruction is actually not executed. However, still, the error is triggered and appears in the console even if the simulation finishes correctly, so it's misleading.

One solution could be to add four more dummy bytes at the end of the text section. https://github.com/esl-epfl/x-heep/blob/a55e7d0b3fa83bd7c746f2705a6c458c108a7e72/sw/linker/link.ld.tpl#L106-L122

When executing or loading from flash, the complete flash memory is initialized to zero, so this problem does not exist. With verilator, assertions are disabled.