idea -- multiple reset modes

[biosbob]

even the simplest Arm MCUs (eg, Cortex-M0) can minimally distinquish between three basic reset modes:

1. a hard reset (power-on, reset-button)
2. a soft reset (initiated programmatically by firmware)
3. a debug reset (initiated through corresponding commands in openocd)

regarding mode 1), i've seen many MCUs further distinquish between power-on, reset-assert, brownout-detect, etc.... perhaps this is something that could find its way into the soc_ctrl IP down the road....

regarding mode 2), some akin to Arm's AIRCR register is currently absent from x-heep.... the effect of a software-initiated reset should put the CPU in the same state as a wakeup from the power_manager -- but without having to actually sleep until an interrupt arises.... perhaps there's a way to "trick" the power_manager by pre-asserting some dummy wakeup condition and then eventually jumping to an entry point like _start; in any event, control will pass through the boot_rom....

regarding mode 3), scripts for loading firmware onto the target (during development as well as production) will need to command a "reset" after loading the image into SRAM or FLASH.... in openocd you can issue a reset halt command, for instance.... right now, my workaround is to simply press BTN_3 on my PYNQ board; but for batch testing it would be essential to have an automated way to achieve this....

as implied by the title, these are suggestions for the future rather than "critical bugs".... as such, let the discussion begin....