cascade
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eschkufz
A Just-In-Time Compiler for Verilog from VMware Research
**Bug report** When _clock.val_ is passed to a module in a generate statement, Cascade throws the error `CASCADE SHUTDOWN UNEXPECTEDLY`. Expected behavior is for the clock to be propagated normally...
The Goal of this was to add 4 bytes to let information be interposed by something else at a message level.
## Overview The newest version of osx is causing trouble for the verilator backend. This is primarily a verilator problem, but the backend should be smart enough to detect a...
## Overview Features we don't currently support: Variables with little-endian ranges ```verilog wire[0:5] x; ``` References with little-endian ranges ```verilog wire[31:0] y; initial $display(y[0:15]); ``` ## Deliverables - [ ]...
## Overview Leaving vmware has left us without a continuous integration solution. ## Deliverables - [ ] Reenable support for continuous integration