Jean-Christophe Léchenet

Results 173 comments of Jean-Christophe Léchenet

In regalloc.ml, there is code to ensure that RA is in conflict with the results. It should certainly be patched. But the unclear part to me is what to do...

Indeed, so it is a problem only for RISC-V, but that means that the problem will be more subtle to fix.

Now I understand, the error is in the RISC-V implementation. We use `ret` like on x86 and on ARM, but on these two platforms the RA is on the top...

On ARM, it is passed in RA then put on the stack and popped from the stack. On RISC-V, it is both passed in RA and read from RA (for...

> Does `returnaddress=stack` makes sense on risc-v? Maybe not.

> On ARM, it is passed in RA then put on the stack and popped from the stack. On RISC-V, it is both passed in RA and read from RA...

Hm, there is still a problem, because when a function is not a leaf function, the compiler correctly decides to save the return address on the stack. But then it...

I also have to rebase on branch risc-v, and to undo the commit adding ra to the callee_saved registers (even if that could make sense, ra contains the return address...

Btw, there is something to be checked about RISC-V, related to the linearization_params. The code was copied from arm, and it should work. But if I'm not mistaken, there are...

I've just rebased on top of #934