xtrx_julia
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Published
20 hours ago •
enjoy-digital
enjoy-digital
Design/Test LMS7002M/FPGA Digital Interface.
Before testing RF, the digital interface of the LMS7002M with the FPGA first has to be validated.
The best is probably to:
- Validate FPGA RX at a low sample rate (with the LFSR pattern that seems present in the LMS7002M and a LFSR checker in the FPGA).
- Validate FPGA RX at a higher sample rate with the same method + delays calibration.
- Validate FPGA TX at a low sample rate by enabling Digital LoopBack of the LMS7002M (DLB) and with a pattern generator on FPGA TX and pattern checker on FPGA RX.
- Validate FPGA TX at higher sample rate with teh same method + delays calibration.
Questions:
- The LFSR polynom does not seem to be specified in the documentation, search online or in fairwaves sources if it can be found something (It seems they calibrated the RX with this method, cf p7 of OsmoDevCon2018_XTRX_status_update.pdf).
- The DLB features seems to be described in the diagram, but not in the register mapping. This probably only consists of configuring the RX Source from TX.
A first version is working at up to 750Mbps for now. This should be enough to start testing RF.
Info from Lime on the LFSRs:
LFSR polynomial is x^15 + x^14 + 1. Sequence length: 2^15 - 1. Initial seed in binary is "100000000000001".
This is how the data are constructed for AI, AQ, BI and BQ channels:
1. AI: Twelve LSBs of LFSR are connected to channel AI;
2. AQ: Twelve inverted LSBs of LFSR are connected to channel AQ;
3. BI: Twelve MSBs of LFSR are connected to channel BI;
4. BQ: Twelve inverted MSBs of LFSR are connected to channel BQ.
Actually, there are two LFSRs - one for each A and B channels. They are enabled when RxFIFO buffers are not full and RX_MUX (0x002A[11:10]) register is set to 0x2. Reset of LFSRs is controlled by SRST_RXFIFO (0x0020[7]) register.