"main_ram Region in IO region, it can't be cached" error attempting to use `rocket` cpu for `sipeed_tang_nano_20k`

[ids1024]

python3 -m litex_boards.targets.sipeed_tang_nano_20k --cpu-type rocket --cpu-variant linux errors with:

ERROR:SoCBusHandler:main_ram Region in IO region, it can't be cached: Origin: 0x80000000, Size: 0x00800000, Mode: RWX, Cached:  True, Linker: False

While there is no such error for a board like gsd_orangecrab (last I checked it built and ran fine on that board).

At first this seems odd, since it uses the same IO region regardless of the board, and the same main_memory start address.

But it looks like the difference is that check_region_is_io/check_region_is_in is checking if the main_ram region is entirely contained within the IO region. On sipeed_tang_nano_20k, it is (there isn't much memory), so this error is produced. While on gsd_orangecrab, the start address of main_memory is within the IO region, while the end address is beyond the end of it.

I'm not sure if litex with rocket is supposed to work with just the 64 Mbit / 8 MB SDRAM on the Tang Nano 20k (I don't know why it wouldn't) or otherwise fit on this FPGA, but the check_region_is_io test doesn't sound right here. I'd expect it should be checking for any overlap with the IO region, and erroring on all boards? Though it does appear to work regardless.

[gsomlo]

Sorry for the (very) late reply.

The most likely explanation for the error is that sipeed_tang_nano_20k does not have DRAM, which is where main_ram is expected to go when provisioning a rocket cpu.

If you open up the platform file for a supported board (e.g., litex-boards/litex_boards/platforms/digilent_nexys_video.py), you'll notice pins connecting the FPGA to DRAM.

There are no such pins (and no DRAM) on the sipeed_tang_nano_20k, and the built-in assumption that there would be results in the error you're reporting.

Also, 8MB sounds like an extremely limited amount of "ram" for a 64-bit CPU, so if one could hack something together to get around the current built-in assumptions, it would only be worth doing as an exercise, as the utility of the result would be rather limited, IMHO...

[ids1024]

There are no such pins (and no DRAM) on the sipeed_tang_nano_20k, and the built-in assumption that there would be results in the error you're reporting.

I don't think that is accurate.

https://github.com/litex-hub/litex-boards/blob/master/litex_boards/platforms/sipeed_tang_nano_20k.py has a section labeled # SDRAM (embedded in SIP, requires specific IO naming) with the pins, and https://github.com/litex-hub/litex-boards/blob/master/litex_boards/targets/sipeed_tang_nano_20k.py has a self.add_sdram() call. The SDRAM is small, an integrated into the FPGA chip, but it does exist, and seems to be configured correctly here.

Also, 8MB sounds like an extremely limited amount of "ram" for a 64-bit CPU

Yes. There's theoretically no reason you can't have a 64-bit CPU with only 8 MB of RAM, but for practical purposes, it probably makes sense to just have a 32-bit bit one.

Though in any case, if check_region_is_io is defined incorrectly, as my understanding was looking at it (and as described above), that should probably be fixed regardless. I guess it shouldn't be all that hard to fix, but does that description sound right?

[gsomlo]

On Mon, Sep 08, 2025 at 07:42:21PM -0700, Ian Douglas Scott wrote:

●ids1024 left a comment (enjoy-digital/litex#2284)

There are no such pins (and no DRAM) on the sipeed_tang_nano_20k, and the
built-in assumption that there would be results in the error you're
reporting.

I don't think that is accurate.

I think "sdram" and "ddram" are treated differently, and it is the latter that's currently required to build Rocket-based LiteX SoCs.