soc/integration: Add support for grouped regions

[cherrypiejam]

Problem: Existing SoC doesn't support mapping a bus to a set of SoC regions. Adding two regions to a single bus will results in a race condition (multiple unconditional assignments in Verilog).

Goal: This patch is to provide support for mapping a bus slave to multiple SoC Regions.

Implementation: Allow add_slave to take a list of SoCRegion to construct a new wrapper type SoCRegionGroup, which its decoder simply reuses decoders defined in every SoCRegion in that list.

Current State & Limitations: Currently it is a proof of concept implementation (as many edge cases are not considered + some hardcoded values). Also, since many other export methods (e.g., export.get_csr_json) assume every region is a continuous region, a helper method flat_regions is used to unwrap each SoCRegionGroup into multiple SoCRegions to comply with existing APIs. I am looking for comments on whether we want this feature and if so whether there's a coherent way to implement this.