[RFC] CSRBone or some MMIO debugging bridge

[FlyGoat]

Somehow related to #1989 I'm trying to implement functionality to control and debug softcore on PL side from PS side.

I ran into an immediate problem that the address space of GP_MASTER on Zynq is not big enough to hold a whole 32 bit address. My current solution to that problem is only mapping CSR address space into GP_MASTER as what we did for pcie, and insert a crossover UART connected to UARTbone. The performance is ..sigh... I'd rather use JTAGBone :-)

So I think we may need a debugging bridge that works for such situation better, I have two ideas in my mind, which would you prefer?

1. Use infra of JTAGBone, but add a frontend that can insert Stream from CSRs, we can call it CSRBone
2. Implement a "Paged remapper" mechanism that allows host to map, say a 4K page, into PCIe or MMIO address space. Controlling registers can also be CSR to simplify the interface design.

Thanks