litepcie
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enjoy-digital
Small footprint and configurable PCIe core
When the SoC is configured with a crossover UART, it could be useful to create a /dev/ttyX device on the Host to access the UART of the SoC directly.
Please visit https://github.com/enjoy-digital/litex/wiki/Feedback-Contribution-Support.
The TLP Packetizers/Depacketizers are using specific classes for the 64/128/256/512-bit datapaths. It should be possible to simplify the code by creating a generic Packetizer/Depacketizer that would support all the supported...
Hello If I want to use this IP for tapeout, Is it ASIC proven or not?
This adds support for Nvidia RDMA to allow for PCIe P2P transfers between the a LiteX device and a Nvidia GPU. The basic API is documented here: https://docs.nvidia.com/cuda/gpudirect-rdma/index.html This has...
Hi all, I'm trying to get litepcie to work on a custom board with a kintex. While looking at the vivado output, I noticed many inter clock paths failing. I...
I am unable to run dma_test with external loopback option from litepcie_util: ./litepcie_util dma_test -w 32 -e litepcie_util prints that 129 TX buffers are sent and zero RX buffers received...
Hi, I am working with the pci_screamer project of your own, and I am experiencing issues with the PCIe PHY from the Xilinx 7 series. I am able to send...
This will complement existing Endpoint implementation. https://en.wikipedia.org/wiki/Root_complex
Does anyone know why the zero-copy mode of litepcie_util would fail specifically when doing the zero-copy DMA test? ``` [sthornington@nuc user]$ sudo strace ./litepcie_util -z dma_test execve("./litepcie_util", ["./litepcie_util", "-z", "dma_test"],...
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Small footprint and configurable PCIe core