litepcie

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Check PCIe bus rescan after loading bitstream.

5

It seems to be possible: https://stackoverflow.com/questions/32334870/how-to-do-a-true-rescan-of-pcie-bus but hasn't been tested.

enjoy-digital

PCIe bus never comes alive

10

I am trying to use LitePCie for my project with the [Trenz TE0712](https://wiki.trenz-electronic.de/display/PD/TE0712+TRM) board. The target and platform files are not there in the [litex_boards](https://github.com/litex-hub/litex-boards), so I made my own...

arindam-bose

If one is running a `litex_term` then disconnects the litex device over a Thunderbolt PCIe bridge (in this case, by disconnecting the thunderbolt cable) the kernel catastrophically hangs. This is...

sjkelly

Add PCIe <-> Wishbone function?

1

How about adding this PCIe Wishbone bridge to litepcie? Basically, it can transfer data between the Host PCIe Bus and SoC's wishbone bus. Code is [here](https://github.com/tongchen126/litepcie_pcie_dma/blob/master/v4-no-sc/wishbone_dma.py). The [LiteWishbone2PCIeDMA](https://github.com/tongchen126/litepcie_pcie_dma/blob/5e6614fa2ff2ba1d5d08d433d54bb0356ec8107b/v4-no-sc/wishbone_dma.py#L161)/[LitePCIe2WishboneDMA](https://github.com/tongchen126/litepcie_pcie_dma/blob/5e6614fa2ff2ba1d5d08d433d54bb0356ec8107b/v4-no-sc/wishbone_dma.py#L239) receives control...

tongchen126

PCIe issues on ADRV2CRR-FMC

2

### Issue Trying to bring up PCIe (gen3 4x and gen3 8x) on this board yielded some unexpected issues and it took some time to find a sequence that works....

smunaut

Support for Xilinx soft PCIe PHY?

3

Hello, I'm wondering if parts of this project can be used to control the Xilinx soft PCIe PHY ([PG239](https://www.xilinx.com/content/dam/xilinx/support/documentation/ip_documentation/pcie_phy/v1_0/pg239-pcie-phy.pdf))? If I'm right, the provided examples only use the hardened-in-silicon IPs...

Elgox2

Move Ultrascale(+) TLP adaption code from Verilog to Migen

2

The AXI streams exposed by the on Ultrascale (+) PHYs are not standardized TLPs. To support the Ultrascale (+) PHYs in LitePCIe (that operates on standardized TLPs), the AXI streams...

enjoy-digital

Non zero-copy dma_test errors after recent DMA refactor

7

After https://github.com/enjoy-digital/litepcie/pull/65, non zero-copy `dma_test` occasionally results in errors: ``` + ./user/litepcie_util dma_test DMA_SPEED(Gbps) TX_BUFFERS RX_BUFFERS DIFF ERRORS 7.03 21569 21441 128 127116032 7.02 43105 42977 128 0 7.02 64641...

maleadt

Would simplify bring-up on some new systems.

enjoy-digital

Using litepcie with LiteFury (SQRL CLE-101)

6

In #38, @enjoy-digital 's recommendation was to try this out with the SQRL CLE-215. I got a LiteFury, which according to [litex-boards](https://github.com/litex-hub/litex-boards/blob/f1e1ae2f7128ea20a31d07b3f0ab256f17582725/litex_boards/platforms/sqrl_acorn.py#L11) is equivalent to the CLE-101, its little sibling....

a3f