litedram

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AxSIZE mismatch?

1

When generating a ram controller with an Axi interface, the awsize and arsize ports are 4 bits wide ```verilog input wire [3:0] user_port_axi_0_awsize, ``` ```verilog input wire [3:0] user_port_axi_0_arsize, ```...

TheZoq2

ulx3s example does not work

3

I'm trying to generate a litedram core for my ulx3s, but am having some trouble. As a first step, I want to see if I can get it working in...

TheZoq2

Setting for user_clk

1

I assume that user_clk is the clock for the AXI interface. Do I have a choice on this clock? Can I set user_clk to any clock value? Thanks

ztachip

DDR4 reads without DQS at high speeds?

1

I noticed that in your USDDRPHY design DQS is used for write only. As I understand it, you do this under an assumption that after DDR calibration procedure DQS read...

alexey-morozov

--top-module 'sim' was not found in the design

5

I used the gen.py file to generate a litedram core, and meanwhile a build_xxxx.sh was generated as well. When I tried to run build_xxx.sh file , it point to a...

CarrolXC

Corresponding verilog testbench for ASIC

1

Hi, I generated a verilog module for the litedram core and now I want to simulate it as as ASIC design, basically I am trying to dummy out those interfaces...

CarrolXC

submodules verilog

2

Hi , I am generating verilog file through gen.py and I did see a top level verilog file in the "build" folder. However , I found I missed all the...

CarrolXC

Hi, I'm integrating LiteDRAM as a standard core into my SoC ([https://github.com/epsilon537/boxlambda/](https://github.com/epsilon537/boxlambda/)). I'm using function *sdram_init()* to initialize SDRAM. This function is not part of the litedram repository, however. It's...

epsilon537

Hi, @mithro and anyone else, I just wanted to know what the typical litedram port sizes are ( in bits I presume) since I need to figure out the L2...

bala122

Wishbone, 2 writes followed by colliding read returns incorrect result, write stuck in FIFO

2

I'm investigating an issue where a specific write-write-read sequence returns an incorrect result. My LiteDRAM core is configured for Arty A7 with a 32-bit wishbone port. I was able to...

epsilon537