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enjoy-digital
Small footprint and configurable DRAM core
As noted in https://github.com/enjoy-digital/litedram/pull/224 there are some features needed to LPDDR4 support. I listed all the things that came to my mind, though some may not be needed. - [...
The Spartan6 S6DDRPHY needs to be refreshed with the simplifications/improvements made to the others PHYs.
Hi, Can the DRAM controller core be generated without a CPU inside? I would like to have an external CPU that performs the initialization and calibration. Thanks in advance.
Hi, Does there exist any documentation on how the native interface sequencing works? It looks similar to the native interface that the Xilinx MIG uses, however, looking at the schematic...
Please visit https://github.com/enjoy-digital/litex/wiki/Feedback-Contribution-Support.
While working on https://github.com/enjoy-digital/litedram/pull/224 I'm using S7DDRPHY as the main reference, and I noticed that it is missing proper preamble/postamble https://github.com/enjoy-digital/litedram/blob/master/litedram/phy/s7ddrphy.py#L214-L215. Currently it sends a full sysclk cycle of DQS...
Improve crossbar's interface to avoid bottleneck when accessing different banks from the same port.
## Identified bottleneck: The VexRiscv SMP cluster is directly connected to LiteDRAM through 2x 128-bit Instruction /Data native LiteDRAM ports:  While doing initial tests with VexRiscv SMP, a bottleneck...
From https://github.com/enjoy-digital/litedram/pull/181: For some modules there seems to be inconsistencies between `tRCD` and `tRP` values in the SPD data, in the SO-DIMM module datasheet and in the datasheet of the...
From https://github.com/enjoy-digital/litedram/pull/181: `tRRD` is specified in `_TechnologyTimings`, so we cannot specify different values for different speed grades. In the datasheet it depends on the speed grade, the highest possible value...
- [ ] Manage bank groups. - [ ] Manage Vref DQ Calibration. - [ ] Add data CRC support (See tn_4003_DDR4_network_design_guide / p4). - [ ] Add DBI support...
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Small footprint and configurable DRAM core