Feature i2 slave r2

[smeenka]

Hereby a proposal for a i2c slave for the stm32.

Goal is to support a slave module with 2 addresses (module address and generic address), which can handle a (limited) burst of transactions from the master (in arbitrary order) in real time. One can prepare 2 read transactions in embassy context (non real time). The transactions are handled in interrupt context (real-time), and the results are collected in a channel. The transactions can be one by one handled in embassy context, and new transactions can be prepared. I did choose to make the buffer size NOT generic. Using generics (like generic_array) for the buffer size makes the code (and error messages) extreme complex.

Functionality is tested with tests i2c_master and i2c_slave in the examples/stm32g0 directory.

Note that this branch is a follow up of branch feature-i2c-slave.