stm32c0 ADC support

[usbalbin]

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Hi! :)

Are there any plans for stm32c0 ADC support?

[usbalbin]

If this is something you want, do you have any pointers for where to begin(just in case I or someone else for that matter wants to give it a try)?

I have little to no experience with embassy, but a little bit of experience with stm32-rs/stm32g4xx-hal

[Dirbaio]

First step is to add the registers to stm32-data. See the ADC peripherals for C0 have no registers field (compare it with G0 which does).

follow the steps in the readme to extract ADC register yamls from all the SVDs. Then diff them between themselves. If you're lucky you'll find the ADC registers in C0 are identical (after cleaning up!) to another family that we already have registers for, in which case you can add an entry mapping the C0 version to that version. If not you'll have to add a new version.

Second step is adding support in embassy-stm32. Here's all the versions mapped to the driver they're using. Again, hopefully it's similar enough to an existing driver that you can reuse it (pointing both families to the same .rs file). If not you'll have to add a new one.

[usbalbin]

Thank you!

@Dirbaio

First step is to add the registers to stm32-data. See the ADC peripherals for C0 have no registers field (compare it with G0 which does). [...]

follow the steps in the readme to extract ADC register yamls from all the SVDs. Then diff them between themselves. If you're lucky you'll find the ADC registers in C0 are identical (after cleaning up!) to another family that we already have registers for, in which case you can add an entry mapping the C0 version to that version. If not you'll have to add a new version.

First off tmp/c031.yaml and tmp/c011.yaml are identical. However diff tmp/g031.yaml tmp/c031.yaml shows very few, yet some differences from what I can tell:

• Different phrasing and or formatting in description fields
• c031.yaml does not seem to have even a single enum
• c031 is missing the bit 24 VBATEN in ADC CCR which RM0490 agrees that it should not have.
• The analog watchdog config registers have bits for 4 extra adc channels(19-22), same in register SMPR for bits SMPSELx, for x: 19..=22.
• Differences in how the bits in CHSELR0 are divided into fields
  • g031 has one 19 bits wide field
  • c031 has 23 single bit fields. From what I can tell c031 better describes what g0x1's RM says but with 4 extra fields for the extra channels (19-22)

Adding support for a new peripheral

[...]

• Identify how many actually-different (incompatible) versions of the peripheral exist, as we must not merge them. Name them v1, v2.. (if possible, by order of chip release date, see here.

Is this close enough that I should merge c031's extra fields for the 4 ADC channels into data/registers/adc_g0.yaml and presumably rename that to data/registers/adc_v5.yaml? If so, should I do anything to ensure those few differences that are, are enforced somehow?