unable to build with latest vivado-2018.2

[oaken-source]

it appears that the arm-xilinx-linux-gnueabi- prefixed toolchain has been removed from the vivado SDK as of version 2017.3. More information (not much though) here:

https://forums.xilinx.com/t5/Embedded-Development-Tools/Unable-to-find-full-path-for-quot-arm-xilinx-eabi-gcc-quot/m-p/827476/highlight/true#M44334

It appears that now the arm-linux-gnueabi- prefixed toolchain should be used instead. I'll give it a try and see if it produces a working build.

[oaken-source]

the uboot checkout appears to need a minor tweak as well, to build with the gcc7 shipped in the vivado SDK, it is sufficient to copy or symlink compiler-gcc5.h to compiler-gcc7.h

[oaken-source]

generating the FPGA stream fails for me with the following output: http://paste.debian.net/1034261/

I'm not entirely convinced that this is due to the vivado sdk version, but it might be related.

[eliaskousk]

I have updated the repo with the following changes:

1. The makefile now uses the linaro toolchain (arm-linux-gnueabihf-) to build the host software (u-boot, linux, dtc) which the latest Vivado versions bundle as you mentioned.

2. Updated the links to the repos in ./boot to point to the latest xilinx u-boot & linux repos (version 2018.2). This applies only to the Zedboard and this way you don't need the gcc7 hack anymore because the latest xilinx u-boot contains the combined gcc define (compiler-gcc.h) which supports gcc7 inside it.

For parallella that hasn't updated its u-boot repo include/kernel files yet your solution with compiler-gcc7.h works fine.

3. Fixed the IP packaging tcl scripts to properly package the risc-v core and now the bitstream build completes.

However I noticed that if I use the small zynq device (010) for the desktop version of Parallella, place and route doesn't complete because the device doesn't fit any more on the device even though the rocket-core is the IMA without the FPU. Maybe if I try a couple of Vivado optimizations it will build on the small device but I currently don't have the time to look into this.

Although the bitstreams for zedboards and parallella build fine again, I'm now having trouble building the legacy riscv-toolchain. Some sub-repos linked to the 2016 commit of the ./ip/rocket-chip/riscv-tool repo are removed or acting strange due to the time it has passed. I also haven't tried rebuilding the HDL of the generated rocket-core, it'll probably break due to the same reasons. (the currently committed sources work fine).

I hope to find enough time soon to review the current state of the rocket-core / risc-v tools. Maybe it's possible to update everything to use a recent enough version of them (not the master branches though since these change really fast and constantly break things).

[oaken-source]

this looks better, the host and bitstream builds, and boots. There are more issues after booting, but I'll post these separately. :)

[eliaskousk]

At last I found time to update everything to build a modern Rocket Core from a fairly recent Rocket-Chip (April 2018). I used most of the scripts and Chisel code I found in the original fpga-zynq repo of UCB and made it work with Vivado 2018.2 (the UCB repo works for up to Vivado 2016.2).

I couldn't solve the boot issues on ZedBoard with a custom built U-Boot & Linux kernel 4.x with Vivado/SDK's 2018.2 ARM GCC7 hardfloat compiler. I also couldn't build a 3.x kernel with GCC7, which would probably work fine with the legacy way of booting stuff with U-Boot.

Thus, for ZedBoard I decided to use PetaLinux 2018.2 which works fine with Vivado/SDK 2018.2 and builds U-Boot & Linux Kernel 4.14 that play nice together and produces a FIT image for the Linux parts (kernel, root filesystem and flatten device tree all in one file). I modified the scripts to use PetaLinux when building the host software for ZedBoard but haven't tested it yet, just gathered the necessary commands in the makefile target.

The old way of building the host software still remains for Parallella, which builds U-Boot & Linux Kernel from Parallella's respective repos (stuck at 2016).

When in ZedBoard's PetaLinux I can now run baremetal RISC-V programs using the fesvr utility which now works fine when built with the updated riscv.baremetal script / target:

cp libfesvr.so /usr/local/lib
./fesvr pk hello

I also wanted to boot RISC-V Linux but I didn't try building it with Poky (the current target in my Makefile might be broken by now). Instead I used the following two files that are inside the home folder of root in this RISC-V root filesystem image of UCB's ZedBoard Image Repo:

• 1. The bbl binary that contains the kernel as a payload
• 2. The root filesystem buildroot.rootfs.ext2

So if you have these files as well you boot the RISC-V Linux kernel on the new Rocket Core with:

cp libfesvr.so /usr/local/lib
./fesvr +blkdev=buildroot.rootfs.ext2 bbl

You can extract the files either by mounting the image or by using this tool or by just booting the complete release from the UCB repo and copying the files in your SD card.