electro-smith
Optimal RPDelay setting
Initially, the RPDelay member of the FMC_SDRAM_TimingTypeDef struct in the SDRAM's PeriphInit method was set to 0, which resulted in an underflow that wrapped to 15 due to a subtraction in the HAL (luckily, it was the top portion of its register, so no other settings were corrupted).
After setting this value to 1, at least one user saw hard faults with particular code configurations, so 1 seems like a risky value. It's not totally clear to me what the proper value should be (and whether it realistically matters). For now, it's been reset to 16 (which will be subtracted by one and result in 15, exactly the same as the initial setting).
According to some quick reverbsc tests, it looks like you can gain up to 5% performance going from 16 to 1, so it's not negligible. In my own testing, no amount of random or sequential writing / reading could get it to crash with a delay of 1, so I'm not quite sure where that issue is coming from.