Kevin Laeufer

Thanks for presenting this list. I generally prefer option `1` because it is the easiest to parse, but I can see now why you might prefer a different option. One...

This proposal has been pending for a long time. How about we all talk this through at the next Chisel meeting on Monday August 29th and make sure we get...

I started implementing this proposal for the firrtl compiler. One thing that needs to be clarified is how bit-indices interact with `DontCare`. I.e., describe how you are allowed to do...

> I can add some clarifying wording to the invalidates section though. I think that is a good idea. Just clarifying that bit-indices are allowed in a `is invalid` statement.

Here is my prototype implementation of this spec change for the `firrtl` compiler: https://github.com/chipsalliance/firrtl/pull/2545 These are my tests, please let me know if any of them disagree with your intention...

> * Remove assumption that each cycle takes 10ms (have a counter mechanism of how many cycles passed between X ms and Y ms) For synchronous designs like the ones...

Just FYI, as far as I know, the 48MHz clock is the only one that can be calibrated via the USB clock.

I think the hardware was mostly done by @daniel-k.

> Nevertheless it is no secret that anybody can sniff the ClientID in 5 minutes or less by using tools like Fiddler. Yes, or you can run something like `strings...