Kevin Laeufer
Kevin Laeufer
Do you know why this is happening? Asserts should only be evaluated if there is a positive clock edge.
Do you know what timestep the assert is triggered at?
> The `assert` statements tell you it was at `0ps`. Can you see a rising edge on the clock at `0ps`? Since these statements are in a `always @posedge clock`...
@terpstra: could your problem be fixed by setting `clock` to `1` from the start instead of `reset`? That would make me a lot happier since we always have a very...
> Hah! I just tried setting clock to 0; ie: I like that fix. Happy to merge if you can update this PR.
@Mergifyio backport 0.5.x
I think this would be a good feature. However, there are some problems that we would have to solve. First, we need to distinguish between: 1. a failure because of...
> I definitely think the circuit should be "idle", such that assert/printf statements do not get toggled. Otherwise, it might muddy the printout in the console That will be hard...
The only way to access the `expectMemory` functionality for now is through the old `PeekPokeTester` compatibility API (in `chiseltest.iotesters`). My minimum requirement for exposing functionality in the mainstream API is...
> I just had a quick look into the Verilator API and found no evidence on how to peek/poke memories... For me this looks like being totally unsupported in Verilator...