Kevin Laeufer

> If there is a method called `expect` that is calling `chiseltest`'s `expect`, the `chiseltest` one is still the one that would get found by `indexWhere(ste => (ste.getMethodName == "expect"...

> If you have any interest for me to include something like this in `chiseltest`, I would do that before resolving this PR. Yeah, I think this would be pretty...

> 1. I opened up a few methods from `chiseltest.Utils`. Some of those methods seem to be only package private. Have you considered putting your new code under a `chiseltest.fixedpoint`...

@mvanbeirendonck Do you want to make a PR with the changes that we discussed above? Any way I can help?

This looks very promising. I left some initial comments. Please ping me when this is ready for a more thorough review.

This is actually a often requested feature. It is a little difficult to implement since it would need to work for all our backends and there might be unexpected interactions...

OK, I think you want all pokes to apply right _after_ the rising clock edge. A "delta cycle" is a Verilog term for the smallest possible time-step in simulation. A...

Looks like the JNI component that we use to load Verilator simulations does not work properly on your Windows system. Unfortunately Windows support (especially for the native simulators) is somewhat...

This was the last such PR that seemed to make chiseltest work on windows for the author: https://github.com/ucb-bar/chiseltest/pull/507

> Verilator 5 added support for SystemVerilog timing constructs, so my understanding is that it's a massive change to the underlying threading implementation. I thought that by default the new...