Kevin Laeufer

This is really cool! I recently wanted an AsyncQueue for one of my designs. Is this the exact implementation used in RocketChip? Are there any unittests you could copy?

For reference/inspiration: - The [migen](https://github.com/m-labs/migen) cdc library: https://github.com/m-labs/migen/blob/master/migen/genlib/cdc.py - The [nmigen](https://github.com/nmigen/nmigen) cdc library: https://github.com/nmigen/nmigen/blob/master/nmigen/lib/cdc.py

> I think before we land a CDC and SVA in FIRRTL, I have no idea on how to test this(and so did in RC). Chiseltest seems to have multi-clock...

As an idea on how to verify the AsyncQueue: You could try to add an assertion that at most on bit in the gray code encoded counter changes at a...

> Maybe @ekiwi can provide some idea, will his formal infra support multi clock domain? Sorry, but I am currently busy and to get the multi-clock support to a usable...

Since `apply` is already overloaded for `UInt`, maybe it would make sense to also just overload it for `EnumType`. This way your example would be even easier to write.

When would someone want to use these FIFOs instead of the Chisel `Queue`? If there are QoR considerations, maybe there should be a way to change `Queue` implementations without changing...

> Any ideas on improving this? Some thoughts: 1) It seems to me like Mux1H should be changed to accept `ChiselEnum1H` instead of a `UInt` directly. 2) You should be...

> For 1, I could send another PR... ok? I would prefer to see everything work together in a single PR. > On 2, you mean the way it's already...

This should only be merged once the RFC is decided: https://github.com/chipsalliance/chisel3/issues/2463