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Published 20 hours ago • verified publisher icon eirikpre

When instantiating, the signal can be listed in the form of wire

Open haidoph opened this issue 1 year ago • 1 comments

hi , 1, When instantiating, the signal can be listed in the form of wire 2, Add this feature to support instantiating multiple modules at the same time, similar to Verilog_mode

tks

haidoph avatar Jan 19 '24 02:01 haidoph

I don't think there's enough information to work with here. Can you be specific about what you are asking here? Maybe code examples?

joecrop avatar Jan 23 '24 18:01 joecrop