`include directive should be allowed anywhere

[DanChianucci]

Currently I get an extraneous input error if the `include is anywhere except file scope.

ie) With UVM, it is common for the uvc package to simple contain includes for individual classes

package my_uvc_pkg;
  `include "transaction_class.svh"   //<-- Error seen here because parser is not expecting `include
  `include "monitor_class.svh"
  // etc...
endpackage

[DanChianucci]

It looks like this same issue extends to all compiler directives. ie `uvm_component_utils(my_component)

[joecrop]

@DanChianucci do you know what is generating the error? Are you using Verilator? If so, it is known to crash hard on most UVM syntaxes. Please see #31.

[DanChianucci]

The bundled antlr parser is generating the error

[joecrop]

Hi @DanChianucci, I finally got around to this. I don't think the problem is the include inside a package. When I rename the file to be transaction_class.sv (removed the h in the extension) the parser is happy. Can you confirm this? If so, this is an easy fix. This file compiles with no errors for me:

package my_uvc_pkg;
    `include "transaction_class.sv"
    `include "monitor_class.sv"
    // etc...
endpackage

class joe extends uvm_object;

    `uvm_object_utils(joe);

    function new(string name = "joe");
        super.new(name);
    endfunction: new
    
enclass joe 

[DanChianucci]

Changing from .svh to .sv fixes Issue #127
ie. "missing FILENAME at '"transaction_class.svh"'

but not the error I am talking about in this issue ie. extraneous input "`include"

[joecrop]

Thanks @DanChianucci, I am able to reproduce this now. There are quite a few places that are missing allowance of includes. I'll try and capture as many as I can find.

[niciki-niciki]

always @( * ) begin
  if ( cond1 ) begin
    case ( sig_key )
      `DEF_CASE1 : sig_name <= 8'b0;
      `DEF_CASE2 : sig_name <= 8'b1;
      default : sig_name <= 8'b1;
    endcase
  end
end

Gives "no viable alternative at input" for: `DEF_CASE1, `DEF_CASE2 and default

It seems that ` sign and default are problems here.

[niciki-niciki]

When instantiating module and using some

...
  .port_name ( `DEF_VAL ),
...

for constant port value - I also get "no viable alternative at input" for ` sign