Adding an SPI Master to the Raven SoC

[sofchet]

Hi,

I want to add an SPI interface to the SoC (hardware level) to communicate with any SPI slave interface. I guess the SPI interfaces that already exist in the Raven design are for other purposes. So I was wondering what would be the best approach to integrate an SPI master interface to the design ? For instance, in case I don't need the Raven_SPI, do you think I can easily just turn it to a general purpose SPI interface ?

Thanks,

[RTimothyEdwards]

I added several components to an update of the Raven chip called Ravenna which we taped out mid-year last year, got back at the end of last year, and have already tested and mostly validated (there were other priorities in the way; the last bit of testing should get done in the next few weeks some time). The new components include the SPI master you're looking for, as well as an I2C master, and a counter/timer module.

To get those modules, see github.com/efabless/ravenna. You can either use the Ravenna project as a base (it is very similar to Raven; essentially just an expanded version of Raven), or copy the SPI master module into your project.

Regards, Tim

[sofchet]

@RTimothyEdwards many thanks for your answer !.

However it seems like the verilog files are not shared yet on the /efabless/ravenna repo. Can you please tell me how can get them ?

I have a kind of related question, but I would open a new issue for it.

Thanks again

[RTimothyEdwards]

Okay, sorry, I didn't realize that the Ravenna repo was only for design support (PCB, assembly, test). The RTL is available on the efabless.com platform (marketplace catalog). I'm not sure how easy it is to get the RTL off the platform, though. It may require some cut-and-paste.

[sofchet]

Thanks a million, I am closing this issue.

[sofchet]

Sorry probably this is not the best place to ask this question, but I got my account review completed and I was granted the full access, however, I am not sure how to get the RTL from the marketplace catalog. On the Ravenna page there seem to be no link that leads to the RTL files.

Should I submit some inquiry ? Thanks,

[RTimothyEdwards]

No problem asking here. . . So from the Dashboard go to the Marketplace, click on the "SoC Platform" tab (the default, I think), and then click on "Ravenna". On that page, below the block diagram, is a button "Add Soft IP". Click that, and enter a project name in the pop-up window or accept the default. A message appears at the top with a link to "Soft Projects" (that you can also reach from the Dashboard). Go to the "Soft Projects" page and find the project listed there. On the same line as the project name, there are a number of buttons including one labeled "CloudV". Click that one. In the CloudV environment, the SPI master can be found under source/simple_spi_master.v. From there, I am not entirely sure of the proper method for copy and paste; there are several menu items under Edit in CloudV (and none of them works with my setup, but I'm using a very old and uncommon window manager under Linux).

[sofchet]

@RTimothyEdwards Many thanks, I was able to integrate the SPI Master from the Ravenna design to the Raven design and perform some simulation.

Based on the simulation waves it seems like the SPI Master is configured to read only 1 Byte at once, for instance the spi_sck coming from the master is right way shut down after 8 periods.

I was wondering what would be the necessary edits to make to be able to write/read 256 bits (32 bytes) at once, with no gaps in between ?

Am I only supposed to edit the state transition verilog part :

where the edit consists in transitioning to the finish state after 255 counts, rather than the 7 counts set through the nbit register.

Or there are much more things into it ?

Thanks