mixed language support (vhdl/verilog)

[dsula]

Description

I was wondering if mixed language support could be officially added to openlane2.

Proposal

Openlane2 already has the capability to read in VHDL files using the VHDLClassic flow. Hopefully support for mixed verilog/vhdl might not be too hard to add, such that both VERILOG_FILES and VHDL_FILES can be specified in the configuration file at the same time.

[donn]

This is on our radar.

For others who want this feature, please react 👍 to the original post as it will help me get it prioritized.